Reading for Nov 15:
 

Horowitz,   Sec.  8.28-8.29,  8.33-8.35.
Hayes and Horowitz:   pp. 350-361.
Also TTL Cookbook,   pp.217-227, "Divide-by-N counters"   (There are several copies in Room 219; please use there.)

Problems due Nov. 17:

Additional Exer. (p. 556) 2 and 4.

    13.5  Fabricating a CMOS NAND

    A.   Using one 74xx00 and one 74xx02, design, construct, and test a circuit which implements the function Q = (A+B)*(A+C)

       (Note: A means "not A", etc.;    "xx" indicates LS, C, or nothing)
 

    B.   Use one 74xx00 to make a device which determines if a 3-bit input number is 0,1,2,4,or 6 (Q=1), or 3,5,or 7 (Q=0).
 

14.1    NAND latch

14.2    D - Flip-flop        (74HC74)

14.3    JK - Flip-flop       (74HC112)

Week 10:
         14.4    Counters from FF's
         14.5 a,b    Switch bounce
         14.6    Shift register         (74HC175)

    plus part of   Lab 15:     Counters