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Maryland
UVa
Orsay
Click
on LAL logo above to go to the L2beta
page at Orsay.
This page contains current and archived information relating to
the DØ Level 2 beta
processor project. The beta
processors will initially complement the existing Alpha
CPU cards in the DØ
Level 2 Trigger system and will ultimately provide a more
flexible and powerful upgrade path for present and future computing
needs.
Project Leaders: Bob
Hirosky (hirosky@Virginia.edu
), University of Virginia
&
Pierre
Petroff (petroff@lal.in2p3.fr
), Laboratoire de l'Accélérateur
Linéaire
Firmware/Technical Coordinator: Bernard
Lavigne ( lavigne@lal.in2p3.fr
),
Laboratoire de l'Accélérateur Linéaire
L2
Consultant: Drew Baden (drew@physics.umd.edu), University of
Maryland
beta Testing:
Patrice Verdier (verdier@lal.in2p3.fr),
Laboratoire de l'Accélérateur Linéaire
Email the L2Beta mailing list at
D0L2Beta@fnal.gov
To
join the mailing list contact Bob Hirosky (hirosky@Virginia.edu)
NEW TDR See Link Below in "Overview Documents"
L2beta group meetings will be held via video conference each Tueday from 9:30-11:00 EST. To be added to conference collaboration contact Bob Hirosky (hirosky@Virginia.edu).
L2beta TDR (last update Aug, 2005 - version 3.2.2)
OLD Documents/Presentations
L2beta technical report v1.4 (April 2000) [to be updated by CPCI design above]
L2beta Presentations ARCHIVE
This section contains links relevant for the design phase of the L2beta. The specification information below will be updated frequently as the project proceeds. The following technical documents superceed any older documentation on the functions and hardware requirements for the Level 2 processors.
D-Zero Magic Bus Document (Last Update Dec 29, 2001)
D-Zero L2Alpha Firmware/FPGA Document (Last Update June 27, 2001) THIS DOCUMENT HAS BEEN REPLACED BY THE TDR ABOVE.
Includes: CPCI specifications and technical resources, single Board Computers, extender cards, prototyping cards, etc.
LAL Design page
Schematics
and Layout Art(Local)
The adapter card mechanical features have been design by Thales. This includes the front panel, rails, and board stiffeners.
University of Michigan Alpha Page. Contains links to schematics, parts documentation, and artwork
L2Alpha Front Panel Dimensions (pdf) (autocad DWG file)
L2Alpha firmware listings
PIO Firmware Schematics (preliminary)
D-Zero TSI Firmware Schematics
CDF TSI Firmware Schematics
Broadcast CPLD VHDL Code
Broadcast FPGA Firmware Schematics
SBC: Advantech MIC-3385 (Data Sheet) (Detailed Manual)
Single/Dual PIII up to 933 MHz
Processor bus up to 133MHz
64-bit/66-MHz local PCI bus
Power REQUIREMENTS
PCI-2-PCI Bridge Chip: INTEL 21154
Memory/PCI Controller Chipset: INTEL 840
Intel 840 chipset home
PCI hub Data Sheet & update
Memory Controller Data Sheet
Rear I/O module accessory manual
Front panel mechanical drawings
PCI Interface: PLX 9656 (Data Sheet) (Detailed Manual - email for details)
64-bit PCI Master/Slave interface chip
The 9656 privides the same register maps and supports the same local bus as the 32-bit 9054 chip (Data Sheet) (Detailed Manual)
Main FPGA: Xilinx Virtex XCV405E (Detailed Manual)
Virtex Series Pages at Xilinx
I/O Pins: 404
Block Ram: 70KB
Link to Xilinx Virtex CORE Solutions page
Virtex-EM page with applications notes on block RAM (including fast FIFOs)
L2Alpha Revision D Schematics and Production Info (UMich) (Local copies)
L2Alpha MBus arbitration revision
Summary of Alpha Specs from Jim Linnemann (PDF) (MSWORD) - a brief overview
DØ Alpha J2 Connections
ALPHA PC164 Technical Reference Manual
Universe II Manual
DØ VME Crate information
Compact PCI standards summary
PMC Standards Document
VME Standards
VMEbus FAQ
VME64 Pin Assignments
VIPA home page
Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices TB363.pdf from Intersil
View Fermilab electrical safety requirements HERE
Progress on the L2beta will be closely followed by an Oversight Committee composed of the following members: Jim Linnemann(chair), Hal Evans, Rick Kwarciany, Bob Hirosky
The charge to the committee can be found here (msword) (pdf)
Oversight committee meetings will be held Thursdays at
2pm EST as required.
Minutes are available here.
L2beta technical report v1.4
Mechanical Description & Assembly Drawing
Electronics Description
L2beta Presentations ARCHIVE
Charge to committee (pdf) (msword)
Review committee's report
Reply to committee: Change to a CompactPCI-processor design (ps) (pdf)
This page maintained by: Bob Hirosky