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| Technical Specifications Table | |
|---|---|
| Packaging | 6U-high, 1U-wide VME unit |
| Inputs | 128 ECL/LVDS inputs, 110 Ohm impedance |
| Double hit resolution | 5 ns |
| Acquisition modes | Trigger Matching Mode; Continuous Storage Mode |
| Built-in memory | 32 kwords deep Output Buffer |
| Trigger Window Width | Programmable from 25 ns to 100 µs |
| LSB | 800, 200, 100 ps (selectable) |
| Dynamic Range | 104 µs (200 ps and 800 ps LSB); 52 µs (100 ps LSB) |
| RMS resolution | <320 ps @ 800 ps res.
<140 ps @ 200 ps res. <80 ps @ 100 ps res. |
| Integral non linearity | <0.3 LSB @ 800 ps res.
<1 LSB @ 200 ps res. <1 LSB @ 100 ps res. |
| Differential non linearity | <0.2 LSB @ 800 ps res.
<0.3 LSB @ 200 ps res. <0.5 LSB @ 100 ps res. |
| Interchannel Isolation | ≤0.7 LSB |
| Offset spread | <2 ns |
| EXT TRIGGER input | Two LEMO 00 bridged connectors, ECL signal, 110 Ohm |
| Clock source | Internal (40 MHz) or External (on Control connector), dip switch selectable |
| Control inputs | active-high, differential ECL input signals:
RST: resets Output Buffer, Status and Control registers. CLR: FAST CLEAR of TAC sections rising-edge active, differential ECL input signals: CLK: external clock TRG: trigger for the TDC latching |
| Control outputs | differential ECL output signal:
OUT_PROG: control output signal, programmable via the out prog control register |
| Displays | DTACK: green LED; lights up at each VME access.
PWR: green/red LED; green: power ON, red: failure status. TERM: green LED; control bus termination ON. FULL: red LED; memory full. ERROR: red LED; TDC global error. DRDY: yellow LED; at least one datum in the output buffer |
| VME | Addressing modes: A24, A32, MCST
Data transfer modes: D16, D32, BLT32, BLT64, CBLT Readout rate: 33 Mb/s |
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